1. Technical Field
This disclosure relates to clock receivers and more particularly, to clock receiver circuits, which receive fully differential clock signals and create controlled clock pulses from each transition.
2. Description of the Related Art
Higher clock rates for clock devices, such as clock receivers, are desired in integrated circuits where performance criteria is increased from one generation of devices to the next. For example, with the advent of double data rate (DDR) synchronous dynamic random access memory (SDRAM) new requirements for the clock receiver arise. These goals include:
A: The delay matching between a rising clock edge to an internal clock with a falling clock edge to an internal clock (with double rate) becomes more important; and PA1 B: The AC-impedance of positive and negative clock input pins should match very well.
Referring to FIG. 1, a standard differential amplifier based receiver 10 does not fulfill requirements A and B very well. The impedance of the internal nodes OUTN and OUTP differ by orders of magnitude so the effect of Miller-coupling is much larger for input VINP (e.g., CK). (For large systems, this makes it difficult for a System Clock driver to supply a good symmetric clock signal).
As shown in FIG. 2, clock signals CK and /CK are received by differential amplifier 20. Pulse generator circuits 22 use a pulse created from a positive edge, and this pulse, together with a pulse created from a inverted negative edge (by inverter 23), are used (by employing an OR function 24) to create a double data rate pulse. This structure, however, may not satisfy goals A and B in every case. The circuit of FIG. 2 includes an additional inverter 23, which can create timing mismatches.
To attempt to fulfill goals A and B, structures such as the one illustratively shown in FIG. 3 have been proposed. This structure includes two differential amplifiers 30. The CK and /CK signals are input to opposite input nodes of each amplifier 30. Pulse generators 32 create pulses on each rising edge of the output of the amplifiers 30. The outputs are ORed by OR function 34 to provide a double rate output. The drawback of this structure is the high current consumption (due to the second pulse generator and second amplifier) and the two separate pulse generators 32 used give rise to timing mismatches.
Therefore, a need exists for a clock receiver, which provides symmetric or matched delay output clock pulses and minimizes power consumption.